A challenge to designing an interface to synchronous DRAM (SDRAM) is managing the timing requirements of the SDRAM over the full range of operating conditions of the driving circuit. When implemented in an ASIC, the driving circuit's timing will vary with temperature, voltage and fabrication process variation. A design that attempts to meet SDRAM's timing requirements at one extreme of the ASIC's operating conditions may not meet the timing at the other extreme of the conditions. A method is needed to create timing that is largely independent of these conditions.
The timing of an SDRAM requires that data signals be stable within a window of time before and after the rising edge of the SDRAM's clock. The stable time before the clock's rising edge is called the setup time; the stable time after the clock's rising edge is called the hold time. Inside an ASIC, the circuits that generate data use a clock's rising edge as a timing reference. Thus data signals have a timing relationship to the clock. As the ASIC's operating conditions change, that timing relationship also changes. This presents a problem when attempting to match the SDRAM's timing requirements, which are fixed.